IMPORTANT to all devices: 1. The PSB was used for user to set/reset CPU's configuration data. Every bits of the PSB usually has the following meanings, unless otherwise specified. bit=1 means programmed, set the flash/rom bit to logic 0. bit=0 means Not-Programmed, keep the flash/rom bit to logic 1(the erased status). ==AMIC 0. A25L032 The Checksum command will display its two status bytes on the LCD display, just at the left side of the slave's ID position. ==Dallas== 0. DS1992/1993 User has to build a 2-pin resistor pluger and plug it at the pin3 and pin4 of the JP31 terminal on the DIP48 module(or any module which has JP31 available). 1234 xxxx <--JP31 G || N || D |R(18K) || \/ The GND pin of DS1992 goes to pin1(the leftmost pin)of the JP31, the signal pin of DS1992 goes to pin2(and pin3) of the JP31, a 18K resistor was wired between pin3 and pin4(VCC) of the JP31. ==ATMEL== 14. AT90USB82/162 \ PSB={(--,--,B12,B11, B02,B01,L2,L1), (-,-,-,-, HWBE,BODL2,BODL1,BODL0), \ (FUSE HIGH BYTE), (FUSE LOW BYTE). The default value of the PSB should manually set to {$00,$08,$26,$9D}. 13. AT91SAM7S64/128/256 The default value of the PSB was set to {$00,$00,$00,$00}.??? \ PSB={(--,--,--,--, Secure,--,Fuse1,Fuse0), (Lock[15..8]), (Lock[7..0])} 12. ATMega48/88 \ PSB={(--,--,B12,B11, B02,B01,L2,L1), (--,--,--,--, --,BOOTSZ1,BOOTSZ0,BOOTRST), \ (FUSE HIGH BYTE), (FUSE LOW BYTE) The default value of the PSB should manually set to {$00,$06,$20,$9D}. The Fuse and Lock bits position in PSB is: bit[31 30 29 28 27 26 25 24] [23 22 21 20 19 18 17 16] - - B B B B L L - - - - - B B B - - L L L L B B - - - - - T T T - - B B B B 2 1 - - - - - S S R - - 1 1 0 0 - - - - - Z Z S - - 2 1 2 1 - - - - - 1 0 T * * * * Note*: only in Mega88/168 bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] R D S W E B B B C C S S C C C C S W P D E O O O K K U U K K K K T E I T S D D E D O T T S S S S D N E O A L L L I U 1 0 E E E E I N N V E E E V T L L L L S E V V V 8 3 2 1 0 B 2 1 0 L 11. ATMega2313 \ PSB={(--,--,--,--, --,--,LB2,LB1), (--,--,--,--, --,--,--,SELFPRGEN), \ (FUSE HIGH BYTE), (FUSE LOW BYTE) The default value of the PSB should manually set to {$00,$00,$20,$9B}. The Fuse and Lock bits position in PSB is: bit[31 30 29 28 27 26 25 24] [23 22 21 20 19 18 17 16] - - - - - - L L - - - - - - - S - - - - - - B B - - - - - - - E - - - - - - 2 1 - - - - - - - L - - - - - - - - - - - - - F - - - - - - - - - - - - - P bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] D E S W B B B R C C S S C C C C W E P D O O O S K K U U K K K K E S I T D D D T D O T T S S S S N A E O L L L D I U 1 0 E E E E V N N E E E I V T L L L L E V V V S 8 3 2 1 0 2 1 0 B 10. ATMega162 \ PSB={(--,--,B12,B11, B02,B01,L2,L1), (--,--,--,M161C, BODL2,BOLD1,BODL0,--), \ (FUSE HIGH BYTE), (FUSE LOW BYTE) The default value of the PSB should manually set to {$00,$00,$66,$9D}. The Fuse and Lock bits position in PSB is: bit[31 30 29 28 27 26 25 24] [23 22 21 20 19 18 17 16] - - B B B B L L - - - M B B B - - - L L L L B B - - - 1 O O O - - - B B B B 2 1 - - - 6 D D D - - - 1 1 0 0 - - - 1 L L L - - - 2 1 2 1 - - - C 2 1 0 - bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] O J S W E B B B C C S S C C C C C T P D E O O O K K U U K K K K D A I T S O O O D O T T S S S S E G E O A T T T I U 1 0 E E E E N E N N V S S R V T L L L L N E Z Z S 8 3 2 1 0 1 0 T 9. AT24RF08 The byte #10..#15 of the APP area(buffer address $40A..$40F) was bypassed during the "Verify" and "Write" command. The chip's size totally is $420 bytes. 8. Tiny10/11 \ PSB={(--,--,--,--, --,L2,L1,--), (--,--,--,FSTRT, RSTDISBL,CKSEL[2..0]) The default value of the PSB should manually set to {$00,$03}. Its Fuse and Lock bits position in PSB is: bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] - - - - - L L - - - - F R C C C - - - - - O O - - - - S S K K K - - - - - C C - - - - T T S S S - - - - - K K - - - - R D E E E - - - - - 2 1 - - - - T I L L L - - - - - - - - - S 2 1 0 7. Tiny12 \ PSB={(--,--,--,--, --,L2,L1,--), (BODLEVEL,BODEN,SPIEN,RSTDISBL, CLKSEL[3..0]) The default value of the PSB should manually set to {$00,$AD}. Its Fuse and Lock bits position in PSB is: bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] - - - - - L L - B B S R C C C C - - - - - O O - O O P S K K K K - - - - - C C - D D I T S S S S - - - - - K K - L E E D E E E E - - - - - 2 1 - E N N I L L L L - - - - - - V S 3 2 1 0 6. AT90S2343/2323/2313/1200 The default value of the PSB should manually set to $20. Its Fuse and Lock bits position in PSB is: bit[07 06 05 04 03 02 01 00] - - S - - L L R - - P - - O O C - - I - - C C E - - E - - K K N - - N - - 2 1 5. AT90S8515 The default value of the PSB should manually set to $20. The Fuse and Lock bits position in PSB is: bit[07 06 05 04 03 02 01 00] - - S - - L L F - - P - - O O S - - I - - C C T - - E - - K K R - - N - - 2 1 T 4. ATMega103 The default value of the PSB should manually set to {$00,$20}. The Fuse and Lock bits position in PSB is: bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] - - - - - L L - - - S - E - S S - - - - - O O - - - P - E - U U - - - - - C C - - - I - S - T T - - - - - K K - - - E - A - 1 0 - - - - - 2 1 - - - N - V - - - - - - - - - E - 3. ATMega16(the only difference is the bit15,14 of FUSE \ PSB={(--,--,B12,B11, B02,B01,L2,L1), (FUSE HIGH BYTE), (FUSE LOW BYTE) The default value of the PSB should manually set to {$00,$66,$1E}. The Fuse and Lock bits position in PSB is: bit[23 22 21 20 19 18 17 16] - - B B B B L L - - L L L L B B - - B B B B 2 1 - - 1 1 0 0 - - 2 1 2 1 bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] O J S C E B B B B B S S C C C C C T P K E O O O O O U U K K K K D A I O S O O O D D T T S S S S E G E P A T T T L E 1 0 E E E E N E N T V S S R E N L L L L N E Z Z S V 3 2 1 0 1 0 T E 2. ATMega8/ATMega8515/ATMega8535(the FUSE bit15 of ATMega8 is RSTDISB.) \ PSB={(--,--,B12,B11, B02,B01,L2,L1), (FUSE HIGH BYTE), (FUSE LOW BYTE) The default value of the PSB should manually set to {$00,$26,$1E}. The Fuse and Lock bits position in PSB is: bit[23 22 21 20 19 18 17 16] - - B B B B L L - - L L L L B B - - B B B B 2 1 - - 1 1 0 0 - - 2 1 2 1 bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] S R W S C E B B B B B S S C C C C 8 S D P K E O O O O O U U K K K K 5 T T I O S O O O D D T T S S S S x D O E P A T T T L E 1 0 E E E E 5 I N N T V S S R E N L L L L C S E Z Z S V 3 2 1 0 B 1 0 T E 1. ATMega128 \ PSB={(--,--,B12,B11, B02,B01,L2,L1), (--,--,--,--, --,--,M103C,WDTON), \ (FUSE HIGH BYTE), (FUSE LOW BYTE) The default value of the PSB should manually set to {$00,$02,$66,$1E}. The Fuse and Lock bits position in PSB is: bit[31 30 29 28 27 26 25 24] [23 22 21 20 19 18 17 16] - - B B B B L L - - - - - - M W - - L L L L B B - - - - - - 1 D - - B B B B 2 1 - - - - - - 0 T - - 1 1 0 0 - - - - - - 3 O - - 2 1 2 1 - - - - - - C N bit[15 14 13 12 11 10 09 08] [07 06 05 04 03 02 01 00] O J S C E B B B B B S S C C C C C T P K E O O O O O U U K K K K D A I O S O O O D D T T S S S S E G E P A T T T L E 1 0 E E E E N E N T V S S R E N L L L L N E Z Z S V 3 2 1 0 1 0 T E ==SyncMOS== 1. SM2965 Its Lock bit(N) and protect position in PSB is: bit[07 06 05 04 03 02 01 00] N N N N - - - P 4 3 2 1 - - - R O T 2. SM59D04G2 \ PSB={InfB1, InfB0} The PSB is the memory content of {InfB1, InfB0}. bit=0 means programmed. Its default value should set to $FF,$A0. During checksum command, the ID shows the {InfB1,InfB0} 3. SM59R16A2 \ PSB={InfB4, InfB3, InfB2} The PSB is the memory content of {InfB4, InfB3, InfB2}. bit=0 means programmed. Its default value should set to $0F,$8F,$55. During checksum command, the ID shows the {InfB4,InfB3} ==WINBOND== 1. W78E58/58B Its special bits in PSB is: bit[07 06 05 04 03 02 01 00] O - - - - E M L S N O O C C V C R C K Y In the buffer, the APROM locates at address 0-7FFF and the LDROM locates at 8000-8FFF. ==ALI== 1. M6759 Its special bits in PSB is: bit[07 06 05 04 03 02 01 00] - L L L - - - - B B B 3 2 1 ==ISSI== 1. IS89C(E)54/58/64/52A/51A Its special bits in PSB is: bit[07 06 05 04 03 02 01 00] - - - - L L L - B B B 3 2 1 ==SST== 1. ST89C5x Its special bits in PSB is: bit[07 06 05 04 03 02 01 00] R R - - S S S - B B B B B 1 0 3 2 1 ==Macronix== 1. MX29L8000T/B There is no way to recover the lock bit status once it's actived(The PSB status will always show active). For an locked chip, it can only be Erased or Programmed through the nWP=VHH control. 2. MX10E8050I Its special bits in PSB is: bit[07 06 05 04 03 02 01 00] C - - - L L L - F O O O I C C C G K K K 3 2 1 The SBYTE and BVEC should be "DOWNLOAD" following the 64K array data. During "READ" command, they will be stored at buffer address 10000H and 10001H. The "UPLOAD" will include both bytes. 3. MX25L12845/6445 This chip has two security mode. The "erase" action will check the mode and decide what to do. It also using character "%" or " " showing on the LCD display, just before the ID code area, to represent its mode. ==Winbond== 1. W49F201, W49L201, W49L401(T) There is no way to recover the lock bit status once it's actived(The PSB status will always show active). For an locked chip, it can only be Erased or Programmed through the nReset=VHH control. 2. W39V040A/FA The PSB has two bits which represent the 16K(bit1) and 64K(bit0) Boot-Lock Size. If both bits are set, the bit0 has higher priority and 64K was locked. ==MicroChip== 1. PIC16F84A/877 and similar devices(F83/CR83/F84/CR84), also the 16F630. 1. The user ID is located at buffer offset $4000(byte address). The EEPROM data is at offset $4200. 2. IC's Checksum shows "CodeSum + CFGW"(has any non-protected) or "CFGW" only(all protected). The Buffer's checksum always shows "CodeSum + PSB". The Checksum command will show the device's CFGW or the user ID of the buffer. 3. "BlankCheck" command checks the CODE, DATA and CFGW. 4. "Verify" command verifies the CODE, DATA and CFGW. 5. PSB was updated by READ, DOWNLOAD and "PSB edit". The CFGW byte in buffer was updated by READ, DONWLOAD, but NOT "PSB edit". IC will only dealing with the PSB, not the data in the buffer. 6. PSB has the opposite bit meansings as stated on the data sheet where a "0" means "programmed". In the PSB, a "1" means "programmed" instead. 7. "UpLoad" command will not upload the PSB value. It means the CFGW word in the uploaded file may has different value from the PSB settings. 8. UserID will only be verified during WRITE procedure, not in the VERIFY command. 2. PIC18F452 and similar devices(242/248/252/258/442/448/452/458) 1. The reserved code memory is 32K($0000-$7FFF). The UserID is at offset $8000-$8007. The config area is at offset $8010-$801F(including the last two bytes for DeviceID). The EEPROM DATA is at offst $8100-$81FF. 2. PSB only include the protect-related bits. All other config bits should be get from "ReadIC" or "DownLoad" command. PSB edit will NOT update the following bits in the buffer. The "Write" command will copy the PSB, not the contents stored in the buffer. PSB bits[23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00] - E - - E E E E W W W - W W W W C C - - C C C C B B B B B R R R R R R R P P P P P P T T T T T T T T T T T T D B 3 2 1 0 R R R R R D B C 3 2 1 0 B 3 2 1 0 3. PSB were updated by READ, DOWNLOAD and "PSB edit". The CONFIG5,6,7 in buffer were updated by READ, DONWLOAD, but NOT "PSB edit". IC will only dealing with the PSB, not the corresponding bytes stored in the buffer. 4. PSB has the opposite bit-meansings as stated on the data sheet where a "0" means "programmed". In the PSB, a "1" means "programmed" instead. 5. "UpLoad" command will not upload the PSB, which means the corresponding bytes in the uploaded file may have different value from the PSB settings. 6. The device ID showing on the LCD display is always the first four UserID read from IC or from buffer. 3. PIC16C54 and similar devices(C52/C54/C54x/C55x/C56x/C57x/C58x) PSB bits[15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00] - - - - - - - - - - - - C W F F P D O O T S S E C C 1 0 1. The CFGW word was stored in the buffer address $0FFF. The CFGW in buffer was updated by READ(meaningless?), but NOT "PSB edit". IC will only dealing with the PSB, not the CFGW stored in the buffer. 2. PSB were updated by READ, DOWNLOAD and "PSB edit". 3. PSB has the opposite bit-meansings as stated on the data sheet where a "0" means "programmed". In the PSB, a "1" means "programmed" instead. 4. The user ID will be copied, verified and checked with the ID bytes stored in the buffer, but not be displayed. Instead, the chip's CFGW will be shown on the LCD during CHECKSUM command. The ID bytes stored in the buffer will be shown on LCD when summing the buffer checksum. 4. PIC12C508 and similar devices(C509/C508A/C509A/CE518/CE519) 1. The CFGW word was stored in the buffer address $1FFE. The CFGW in buffer was updated by READ, DONWLOAD, but NOT "PSB edit". IC will only dealing with the PSB, not the CFGW stored in the buffer. 2. PSB were updated by READ, DOWNLOAD and "PSB edit". 3. PSB has the opposite bit-meansings as stated on the data sheet where a "0" means "programmed". In the PSB, a "1" means "programmed" instead. 4. The user ID will be copied, verified and checked with the ID bytes stored in the buffer, but not be displayed. Instead, the chip's CFGW will be shown on the LCD. The ID bytes stored in the buffer will be shown on LCD when summing the buffer checksum. 1. PIC10F200/202/204/206 1. IC will only dealing with the PSB, not the CFGW byte in the buffer. 2. PSB was updated by READ, DOWNLOAD and "PSB edit". The CFGW byte in buffer was updated by DONWLOAD, but NOT by "READ" and "PSB edit". 3. PSB byte has the opposite bit-meansings as stated on the data sheet where a "0" means "programmed". In the PSB byte, a "1" means "programmed" instead. 4. The Buffer's checksum always shows "CodeSum(0:$FE)" + PSB. The Device's checksum is "CodeSum(0:$FE) or CodeSum(0:$3F)" + CFGW. The Checksum command will show the device's CFGW or the user ID of the buffer. 5. "BlankCheck" command checks the CODE and CFGW. 6. "Write", "Erase" and "Verify" commands will handle the CODE, ID and CFGW. The Reset Vector and OSCCAL will be unchanged. 7. "UpLoad" command will not upload the PSB byte.